Electronic devices incorporating integrated circuits, such as application specific integrated circuits (ASICs), often employ power saving techniques to reduce power consumption and thereby achieve extended battery life. Small, portable devices such as mobile telephones and personal digital assistants (PDAs), for example, typically incorporate circuitry for implementing inactive modes to limit power consumption by logic circuitry. Inactive modes may include stand-by, low power and sleep modes.
Power dissipation in digital circuits, and more specifically in CMOS circuits, is approximately proportional to the square of the supply voltage. Therefore, the most effective way to achieve low-power performance is to scale down the supply voltage. CMOS circuits on ASICs are capable of operating at significantly reduced power levels. In order to avoid increases in propagation delay, however, the threshold voltage of the CMOS devices also is reduced.
The reduction in threshold voltage generally causes an increase in stand-by current due to changes in the sub-threshold leakage current of the MOS devices. The leakage current that flows through an “off” transistor tends to increase exponentially as the threshold voltage of a device is reduced. Moreover, as manufacturing technology evolves to a higher level of integration and the minimum feature capable of being manufactured becomes smaller and smaller, e.g., 90 nm, 65 nm or 45 nm and lower, going to nanotechnology level, gate leakage and sub-threshold leakage become even more problematic. Therefore, electronic devices such as mobile telephones and PDAs that remain in an inactive mode for an extended period of time can exhibit significant leakage current, and cause undesirable drain on battery power during the inactive mode.